1. Field of the Invention
The present invention relates to a nonvolatile storage device that uses a nonvolatile memory such as a flash memory, an information processing apparatus for controlling the nonvolatile storage device, an information processing system comprising the nonvolatile storage device and the information processing apparatus, and a nonvolatile memory controller for controlling the nonvolatile memory.
2. Description of the Related Art
In recent years, as a nonvolatile storage device equipped with a NAND-type flash memory as a rewritable nonvolatile memory, memory cards are being used as the storage medium of digital cameras and mobile phones, and its market is expanding.
Moreover, pursuant to the microfabrication of the semiconductor process, the bit unit price of nonvolatile storage devices has decreased and nonvolatile storage devices are being used as an inexpensive storage device in markets other than memory cards; for example, as memories of SSD (Solid State Drive) used as a substitute of HDD (Hard Disk Drive) or of embedded systems which are directly mounted on a host device, and its application is expanding.
Here, pursuant to the increase in the capacity of memory cards, the amount of data that is handled by digital cameras, mobile phones, digital video cameras and the like as the information processing apparatus for controlling the memory card is also increasing, and, as a legitimate requirement, faster data transfer performance between the memory card and the information processing apparatus and lower power consumption are being demanded.
As one solution of performing the transfer of data faster and with low power, there is a method of reducing the amplitude voltage of the interface signals. The interface voltage of a standard memory card was mainly 3.3 V, but the application of a low interface voltage of 1.8 V has begun.
Meanwhile, contrary to the trend of lowering the interface voltage for achieving faster data transfer performance, the operating voltage of NAND flash memories used in memory cards remains high. Thus, a flash memory requires a voltage of 3.3 V, and the information processing apparatus needs to supply 3.3 V to the memory card. Consequently, there are information processing systems which supply 3.3 V to the flash memory and supply a low voltage of 1.8 V for the interface signals.
This kind of conventional information processing system is now explained with reference to FIG. 20 and FIG. 21. FIG. 20 is a diagram showing the configuration of a conventional information processing system. The information processing system 2001 is configured from a host device 2002 as the information processing apparatus, and a memory card 2003 as the nonvolatile storage device. The host device 2002 and the memory card 2003 connect a voltage line (VDD) 2030, a ground line (GND) 2031, a clock line (CLK) 2032, a command line (CMD) 2033, and a data line (DAT [3:0]) 2034 as interfaces.
FIG. 21 is a timing chart of the respective interfaces in the conventional information processing system shown in FIG. 20. At time t2101, the host device 2002 applies a voltage to the memory card 2003 via the voltage line 2030.
Subsequently, at time t2102, the host device 2002 waits for the voltage level of the voltage line 2030 to sufficiently reach 3.3 V, and then applies a clock to the clock line 2032. The amplitude of the clock line 2032 at this point in time is 3.3 V. The host device 2002 issues an “initialization command” 2110 to the memory card while oscillating the clock.
Here, the host device 2002 includes inquiry information regarding whether the memory card 2003 can change the interface voltage in the “initialization command” 2110. The memory card 2003 returns, to the host device 2002, a “busy response” 2111 indicating that the initialization is not complete, or a “ready response” 2112 indicating that the initialization is complete. Here, the memory card 2003 returns the “ready response” 2112 upon storing information indicating that the interface voltage is changeable.
Once the initialization of the memory card 2003 is complete, the host device 2002 issues a “voltage change command” 2113 to the memory card 2003. The memory card 2003 returns a “voltage change response” 2114 to the host device 2002, and, at time t2103, drives the command line 2033 and the data line 2034 at ground level.
Subsequently, the host device 2002 detects that the command line 2033 and the data line 2034 are being driven at ground level, and, at time t2104, stops the clock supply to the clock line 2032 and drives it at ground level.
The host device 2002 thereafter changes the interface drive voltage from 3.3 V to 1.8 V. The memory card 2003 recognizes that the clock of the clock line 2032 has been stopped and changes the interface drive voltage from 3.3 V to 1.8 V. Here, since the clock line 2032, the command line 2033, and the data line 2034 are being driven at ground level, there is no change in the level of the respective interfaces.
Moreover, the host device 2002 starts the clock supply to the clock line 2032 at time t2105 which is after the lapse of a predetermined time; for example, after 5 ms, from the time that the clock supply to the clock line 2032 was stopped. The amplitude of the clock line signals at this point in time is 1.8 V.
Meanwhile, the memory card 2003 detects that the clock of the clock line 2032 has been oscillated, and, after driving the command line 2033 to 1.8 V at time t2106, stops the drive of the command line 2033 to realize a high impedance state. Since the command line 2033 is pulled up by the host device 2002, it maintains 1.8 V.
Subsequently, at time t2107, the memory card 2003 drives the data line 2034 to 1.8 V, and thereafter stops the drive of the data line 2034 to realize a high impedance state. Since the data line 2034 is pulled up by the host device 2002, it maintains 1.8 V.
Here, the memory card 2003 can detect an abnormality of the host device 2002 in the processing for changing the interface voltage by detecting the voltage level of the command line 2033 before stopping the drive of the data line 2034 at ground level and driving it to 1.8 V. Specifically, in cases where the host device 2002 is still outputting 3.3 V, since the command line 2033 is pulled up and raised to 3.3 V, the memory card 2003 can detect an abnormality by detecting that the voltage of the command line 2033 is higher than 2.0 V.
The interface voltage is changed from 3.3 V to 1.8 V as described above. Subsequently, the host device 2002 issues a “read command” 2115. The memory card 2003 returns a “read response” 2116, and thereafter outputs read data 2117 via the data line 2034. After completing the required data transfer between the host device 2002 and the memory card 2003, at time t2108, the host device 2002 blocks the application of voltage to the memory card 2003 via the voltage line 2030.
As other conventional technologies, Japanese Patent Application Publication No. 2009-199106 discloses procedures for stably switching the interface voltage, and Japanese Patent Application Publication No. S56-123023 discloses technology for blocking the power source of the storage device during non-use. Moreover, as technology concerning a system which changes the power source supply performance of a host device, Japanese Patent Application Publication No. 2008-217147 discloses technology for variably controlling the power consumption of the storage device.
Nevertheless, none of the foregoing patent documents suggest the possibility of a mismatch in the interface voltages between an information processing apparatus and a nonvolatile storage device in an information processing system, or disclose a processing routine for dealing with the occurrence of such a mismatch.
Here, a mismatch of the interface voltages becomes a factor that leads to a failure of the information processing system. For example, in cases where 3.3 V is supplied as the power supply voltage of the IO driver of the host device 2002 and the memory card 2003, and “H” level signals of 1.8 V are input to the IO driver, a through current flows through the Pch transistor and the Nch transistor which are used for the input of the IO driver. This through current leads to unnecessary power consumption, and, if the voltage source of the host device 2002 is a battery, this will lead to the considerable loss of the duration of the battery.